The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly, to an improvement in an element isolation technique of a metal oxide semiconductor large scale integrated circuit (MOSLSI) together with an improvement in a diffusion wiring layer and stabilization of a substrate potential.
Selective oxidation is generally adopted to isolate semiconductor elements from each other in the process for manufacturing a semiconductor device, especially, a MOSLSI. The selective oxidation will be described with reference to an n-channel MOSLSI.
As shown in FIG. 1A, an SiO.sub.2 film 2 is grown on a p-type silicon substrate 1 which has a crystal plane of (100). An Si.sub.3 N.sub.4 film 3 is then deposited on the SiO.sub.2 film 2. A photoresist pattern 4 which corresponds to a prospective element formation region is formed by photoetching. Using the photoresist pattern 4 as a mask, part of the Si.sub.3 N.sub.4 film 3 which does not correspond to the prospective element formation region is etched to form an Si.sub.3 N.sub.4 pattern 3'. Thereafter, boron is ion-implanted to form a p.sup.+ -type region 5 as a channel stopper in the field region (FIG. 1B). After the photoresist pattern 4 is removed, a thick field oxide film 6 is selectively grown by wet oxidation using the Si.sub.3 N.sub.4 pattern 3' (FIG. 1C) as a mask. The Si.sub.3 N.sub.4 pattern 3' and the SiO.sub.2 film 2 are etched, and an element formation region 7 which is isolated by the field oxide film 6 is formed (FIG. 1D). As shown in FIG. 1E, a gate electrode 9 which comprises polycrystalline silicon is formed in the element formation region 7 through a gate oxide film 8. Arsenic is ion-implanted in the element formation region 7 and is thermally diffused to form n.sup.+ -type regions 10 and 11 which are respectively defined as the source and drain. A CVD-SiO.sub.2 film 12 which functions as an insulating interlayer is deposited. Contact holes 13 which correspond to the n.sup.+ -type regions 10 and 11 and the gate electrode 9 are formed in the CVD-SiO.sub.2 film 12. Aluminum wirings 14 are deposited in the contact holes 13 to prepare an n-channel MOSLSI (FIG. 1F).
However, the various drawbacks are presented by the above-mentioned conventional thermal oxidation method for manufacturing the MOSLSI.
FIG. 2 is a detailed sectional view showing a structure when the field oxide film 6 is formed using the Si.sub.3 N.sub.4 pattern 3' as a mask, shown in FIG. 1C. Generally, in the selective oxidation method, it is known that the field oxide film 6 grows to extend under the Si.sub.3 N.sub.4 pattern 3' (region F in FIG. 2). Since an oxidant is diffused through the thin SiO.sub.2 film 2 under the Si.sub.3 N.sub.4 pattern 3' during field oxidation, the field oxide film 6 has a portion D which is a bird's beak and a portion E which is a thick portion along the transverse direction of the field oxide film 6. The length of region F is about 1 .mu.m when the field oxide film 6 of 1 .mu.m thickness is grown under the condition that the Si.sub.3 N.sub.4 pattern 3' and the SiO.sub.2 film 2 have the thickness of 1,000 .ANG. . A width C of the field region cannot be less than 4 .mu.m since the length of the region F is 1 .mu.m when a distance A between the Si.sub.3 N.sub.4 patterns 3' is 2 .mu.m. As a result, a highly integrated LSI cannot be obtained. In order to eliminate the above drawback, a method has been recently proposed wherein the thickness of the Si.sub.3 N.sub.4 pattern 3' is increased and the thickness of the underlying SiO.sub.2 film 2 is decreased to prevent the bird's beak (portion D). Alternatively, another method is proposed wherein the thickness of the field oxide film 6 is decreased to prevent formation of the region F. However, in the former method, the mechanical stress at the end of the field region is increased, resulting in the defective LSI. In the latter method, the field inverted voltage is decreased. Thus, high integration by the selective oxidation method is limited.
When boron is ion-implated to form a channel stopper, boron is transversely diffused during the field oxidation. Part of the element formation region 7 becomes the p.sup.+ -type region 5 as shown in FIG. 3A due to redistribution of boron previously ion-implanted for the channel stopper in the transverse direction during field oxidation. The width of the effective element region is decreased from a width G to a width H. As a result, a current flowing through the transistor is decreased, and the threshold voltage is increased, resulting in the narrow channel effect. This effect is a significant problem when the semiconductor element is micronized. Further, since the p.sup.+ -type region 5 extends transversely, the p-n junction between the n.sup.+ -type region 11 (10) and the p.sup.+ -type region 5 is widened as shown in FIG. 3B. The stray capacitance between the substrate 1 and the n.sup.+ -type regions 10 and 11 is increased. The stray capacitance cannot be neglected when the semiconductor element is micronized.
As described above, various problems are presented in manufacture of an LSI of a high packing density when the selective oxidation method is used. Further, the problems are described with reference to FIGS. 4 to 6.
It is generally difficult to cross an n.sup.+ -type wiring layer 10' and a polycrystalline silicon electrode 9' on the field oxide film 6 (FIG. 4). In order to cross the wiring layer 10' and the electrode 9', the n.sup.+ -type layer 10" must be formed under the field oxide film 6. For this purpose, an impurity such as phosphorus or arsenic must be doped prior to field oxidation. In this case, since the concentration of the impurity is generally high, the n-type doped impurity is out-diffused at the initial period of field oxidation, so that the p-type region on the surface of the substrate may often be changed to an n-type region. When an n-type impurity is diffused in a gate region 1', the threshold voltage of the transistor is decreased. Further, according to the above method, when the n.sup.+ -type region is formed under the field oxide film 6, margin M1 between the n.sup.+ -type layers 10 and 10" and margin M2 between the n.sup.+ -type layers 10'" and 10' must be formed to isolate the n.sup.+ -type layers 10, 10' and 10'". Therefore, the field width becomes as great as M1+M+M2, and a highly integrated circuit cannot be provided.
Further, according to the conventional selective oxidation method, the following problems are also presented which will be described with reference to FIG. 7.
In order to package an LSI pellet, a substrate 1 is mounted on a bed 15 of the package. When the LSI is operated, the potentials of element regions 16.sub.1 to 16.sub.3 for the source, drain and so on fluctuate in accordance with the operation state. In this case, a current flows through the substrate 1 in accordance with changes in the potentials of the element regions 16.sub.1 to 16.sub.3. For example, with respect to the element region 16.sub.1, the current flows through a path of the element region 16.sub.1, a resistor R1, the bed 15, the element region 16.sub.1, a register R2, the bed 15, the element region 16.sub.1, a register R5, the bed 15 and so on when the bed 15 is electrically conductive and the substrate 1 is electrically connected to the bed 15. A potential of the substrate 1 in the vicinity of the element region 16.sub.1 fluctuates in correspondence with a voltage drop due to the current flow described above. However, such a variation in the potential is undesirable for circuit operation. Especially, when the voltage of the element region 16.sub.1 is changed and when the potential of the element region 16.sub.2 is not changed, the potential of the substrate 1 in the vicinity of the part between the element regions 16.sub.1 and 16.sub.2 is changed. Thus, electrical characteristics of the element vary in accordance with points on the pellet, which is inconvenient. For stabilizing the electrical characteristics, the internal resistance of the substrate must be decreased. However, the resistance of resistors R5 to R8 and resistors R9 to Rll is determined by the impurity concentration of the substrate and the film thickness of the substrate which is connected to the bed. In general, the resistance of the resistors R5 to R8 and R9 to R11 is about hundred ohms to several hundreds of ohms. Therefore, the internal resistance can hardly be decreased. The resistance of the resistors R1 to R4 can be decreased regardless of the electrical characteristics of the element since these resistors provide the internal resistance of the field region 6. However, according to the conventional method described above, the concentration of the p-type impurity cannot be increased, so the resistance is very high. For example, the impurity is ion-implanted in the field region at a dose of 1.times.10.sup.13 cm.sup.-2, and the sheet resistance of the p.sup.+ -type layer is about 10 kilohms/.quadrature..